HEPIC Traineeship Program

I am a graduate student at Stanford University pursuing my MS in Electrical Engineering. I hold a B.S. in Electrical and Computer Engineering from Cornell University, Class of 2021. I am passionate about developing solutions at the intersection of semiconductors and large-scale applications. My past research experiences at both national and university laboratories were in sensing/readout chip design, ML/DL accelerators, FPGA reconfigurability, autonomous flight, nanofabrication, and plasma nanosynthesis. I have also interned in several industries: semiconductors (Intel), accelerated computing (Cornell CAC), and defense (Lockheed Martin-Sikorsky RMS). 

My HEPIC Traineeship work is under Fermi National Accelerator Laboratory’s ASIC group in the Detector R&D division. In the upcoming fall 2023, I will be pursuing doctoral studies building photonic integrated circuits at the Lightwave Research Laboratory, Columbia University.

I am currently a 2nd-year PhD student at the University of California, Santa Cruz in the Electrical and Computer Engineering Department (ECE). My thesis work involves characterization of electronic materials and devices, medical and molecular imaging technologies, and instrumentation for radiation detection applications. My research interests include front-end readout electronics, integrated circuit design, pixel readouts, and photon counting X-ray imagers.

I am a first year PhD student in Stanford’s Electrical Engineering department, and I am interested in designing hardware systems. When I was an undergraduate student, my goal was to understand how each component of a computer worked. I studied how semiconductor devices worked, how they were manufactured, how they can be used to create analog and digital circuits, and finally how the whole system comes together to make a computer. As a graduate student, I now hope to use this knowledge to design new and interesting systems. I am currently interested in analog and optical fiber communication systems.

My research interest is to use tools in solid state physics and IC design to save lives and/or discover something about the universe. I am a Stanford student majoring in Engineering Physics (‘23), doing a coterm in EE (‘24), and an incoming PhD student in EE. In the HEPIC traineeship program, I will improve my knowledge in solid state physics, IC design, and gain teamwork experience, which will be a fantastic preparation for my PhD studies. 

Efabless caravel frame with passive structures for carbon nanotube testing and Skywater 130 amplifier design for carbon nanotube readout. 

I am currently pursuing a master's degree in the Electrical and Computer Engineering Department at UC Davis, where I completed my Bachelors of Science in 2022. My research is primarily centered on mixed-signal integrated circuit (IC) design, with a particular emphasis in applications for radiation detectors. When I am not on campus, I enjoy spending time with my friends and family.

I am a first-year electrical engineering master's student at UC Davis, part of an accelerated master's program. My research area is in analog IC design, particularly PMIC and power-ICs. My current research project is proofing and designing an analog processor to compute the SoftMax activation function to accelerate convolutional neural network computation. My goal is to broaden my understanding of IC design into ASIC design, as well as get hands-on experience with IC CAD tools from theory to tape-out.

My passion in the research of electrical engineering is in both low-power analog as well as terahertz and millimeter wave IC designs. I took courses in power electronics, RFIC, and digital IC. On Cadence Virtuoso, I designed a large bandwidth 10dB amplifier at 200 GHz using a 45 nm process NMOS and an oscillator for that frequency. I also fabricated impedance transformers of a 3-stage cascaded microstrip lines in a dark room. I aim to return to academia as my career and focus on research in terahertz-speed ADC and DACs, as well as other RFIC and analog IC related fields.

project: Design and revise PMOS comparator and bootstrap sampling circuits for a 12 bit SAR ADC

project: Realizing parts of in-pixel ADC  

project: Transimpedance amplifier for low input impedance applications

project: Design a digital to analog converter circuit in TSMC 28nm

project: Development a deep cryogenic process design kit

project: Redesign the TDC for the Mu2e-II upgrade project

project: To integrate a time-to-digital converter (TDC) into the pixel array

project: Measurement, characterization, and modeling of single transistors at cryogenic temperatures

My interests include analog sensors, embedded systems, and more generally systems that encourage multi-disciplinary thinking. Through the HEPIC traineeship program, I had the opportunity to work with the IC design team at the SLAC National Accelerator Laboratory. My main project involved the complete design (from architecture selection to post layout verification) of a dynamic voltage comparator for a future SAR ADC design. I also implemented the gm/ID circuit optimization workflow I learned at Stanford to optimize reference buffers that dominated power consumption in an ADC replicated over 10K times in an ASIC. My mentors/supervisors (Aldo and Llorenç) were very engaged with my efforts and often provided constructive feedback that helped me build new ideas and improve my work execution. The positive team culture and combined professional expertise within SLAC's IC design team creates the perfect environment for trainees to develop their technical skills and enjoy the process. No trade-offs there!

My passion in the research of electrical engineering is in both low-power analog as well as terahertz and millimeter wave IC designs. I took courses in power electronics, RFIC, and digital IC. On Cadence Virtuoso, I designed a large bandwidth 10dB amplifier at 200 GHz using a 45 nm process NMOS and an oscillator for that frequency. I also fabricated impedance transformers of a 3-stage cascaded microstrip lines in a dark room. I aim to return to academia as my career and focus on research in terahertz-speed ADC and DACs, as well as other RFIC and analog IC related fields.

project: eFPGA Firmware Development and Testing

My research focuses on the design and implementation of the QPix charge readout architecture for future large-scale particle detection experiments such as DUNE. My work includes developing simulation frameworks for modeling large-scale chip networks, as well as integrating the QPix analog front-end with existing LArPix digital systems through my traineeship with the HEPIC program. During my HEPIC traineeship at Lawrence Berkeley National Laboratory, I worked on integrating the QPix analog charge readout with the LArPix digital backend. The experience gave me my first hands-on exposure to digital IC design and mixed-signal simulation, expanding my work beyond analog design. I now continue to use these tools in my research on QPix/LArPix integration and large-scale chip network simulations.

project: 28nm Device Array Testing

project: Gampix pixel ADC

project: Literature review on carbon nanotubes